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[SM-Grimoire-Bugs] [Bug 15962] New: Verilog Hardware Design Language Compiler and Simulator (Requires sha1 hash)
- From: bugzilla-daemon AT bugs.sourcemage.org
- To: sm-grimoire-bugs AT lists.ibiblio.org
- Subject: [SM-Grimoire-Bugs] [Bug 15962] New: Verilog Hardware Design Language Compiler and Simulator (Requires sha1 hash)
- Date: 12 Apr 2011 00:45:45 -0000
http://bugs.sourcemage.org/show_bug.cgi?id=15962
Summary: Verilog Hardware Design Language Compiler and
Simulator (Requires sha1 hash)
Product: New Spells
Version: test
Platform: All
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P3
Component: Spell Submission
AssignedTo: sm-grimoire-bugs AT lists.ibiblio.org
ReportedBy: Belxjander AT gmail.com
SPELL=iverilog
VERSION=0.9.4
SOURCE=verilog-${VERSION}
SOURCE_DIRECTORY=${BUILD_DIRECTORY}/${SOURCE}
SOURCE_URL[0]=ftp://icarus.com/pub/eda/verilog/v0.9/${SOURCE}.tar.gz
SOURCE_HASH=volatile
BUILD_API=2
WEB_SITE=http://icarus.com/
ENTERED=20110411
LICENSE="GPL(2+)"
SHORT="Icarus Verilog is a Verilog simulation and synthesis tool. "
cat << EOF
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an
intermediate form called vvp assembly. This intermediate form is executed by
the `vvp'' command. For synthesis, the compiler generates netlists in the
desired format.
EOF
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- [SM-Grimoire-Bugs] [Bug 15962] New: Verilog Hardware Design Language Compiler and Simulator (Requires sha1 hash), bugzilla-daemon, 04/11/2011
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