[SM-Grimoire-Bugs] [Bug 15962] New: Verilog Hardware Design Language Compiler and Simulator (Requires sha1 hash)

bugzilla-daemon at bugs.sourcemage.org bugzilla-daemon at bugs.sourcemage.org
Mon Apr 11 20:45:45 EDT 2011


http://bugs.sourcemage.org/show_bug.cgi?id=15962

           Summary: Verilog Hardware Design Language Compiler and
                    Simulator (Requires sha1 hash)
           Product: New Spells
           Version: test
          Platform: All
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P3
         Component: Spell Submission
        AssignedTo: sm-grimoire-bugs at lists.ibiblio.org
        ReportedBy: Belxjander at gmail.com


SPELL=iverilog
         VERSION=0.9.4
          SOURCE=verilog-${VERSION}
SOURCE_DIRECTORY=${BUILD_DIRECTORY}/${SOURCE}
   SOURCE_URL[0]=ftp://icarus.com/pub/eda/verilog/v0.9/${SOURCE}.tar.gz
     SOURCE_HASH=volatile
       BUILD_API=2
        WEB_SITE=http://icarus.com/
         ENTERED=20110411
         LICENSE="GPL(2+)"
           SHORT="Icarus Verilog is a Verilog simulation and synthesis tool. "
cat << EOF
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
compiler, compiling source code writen in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an
intermediate form called vvp assembly. This intermediate form is executed by
the `vvp'' command. For synthesis, the compiler generates netlists in the
desired format. 
EOF

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